Conventionally, there has been an art in which a computing circuit is composed by employing a variable logic unit, for example, that known as FPGA (Field Programmable Gate Array) or FPLD (Field Programmable Logic Device) (for example, see Japanese Patent Application Laid-Open Publication No. 10-111790, hereinafter Patent Document 1). Also, there have been conventional arts relating to a method, structure, property, operation, and forming method onto CMOS, of a switch that realizes two stable states (bistable states), (for example, see “On a Micro-Electro-Mechanical Nonvolatile Memory Cell”, written by Beat Halg, IEEE published in October 1990, “IEEE Transactions on Electron Devices”, pp. 2230-2236, published by IEEE, and “Breaking the Resistivity Barrier”, written by R. T. Edwards and C. -J. Kim, IEEE published in July 2001, “Proceedings of the Third NASA/DoD Workshop on Evolvable Hardware”, pp. 167-171, published by IEEE, as Non-Patent Documents 1 and 2). In addition, conventionally, a switch element for FPGA comprising wirings that are movable by the coulomb force, and capable of changing connections with low voltage, is provided (for example, see Japanese Patent Application Laid-Open Publication No. 11-330254, hereinafter Patent Document 2).